Forum Discussion
Altera_Forum
Honored Contributor
16 years agoA few things to note
1 - Any change to the design will produce in a different compilation result. You can partition the design and lock down the partitions so they don't change between compilations if you'd like. 2 - I would first analyze your SRAM interface. Does it provide proper timing by design of all the data, address, and control signals? 3 - If the SRAM interface design is correct, proper timing constraints should take care of your problem. It's likely that you just haven't got the timing constraints quite right for your design. If you are willing to post your design, we could take a look at it. Jake