Combinatorial minimization

Dear all,

I tried a simple Verilog code for a combinatorial function with 6bit input and 7bit output.

I describe the logic with a case statement. Since only six input cases are significant (the circuit referes to an encoder without priority) I set the output to x using the default statement.

The code is the following

module prova2 (A,Y);
input  A; output  Y;
wire  A; //wire  Y;
reg  Y;
// Using this case results in 13 LE used 5.6 ns delay
always @(A)
begin
case (A)
6'b000001 : Y <= 7'b1000000;
6'b000010 : Y <= 7'b1111001;
6'b000100 : Y <= 7'b0100100;
6'b001000 : Y <= 7'b0110000;
6'b010000 : Y <= 7'b0011001;
6'b100000 : Y <= 7'b0010010;
default   : Y <= 7'bxxxxxxx;
endcase
end
/*
// Using the minimized functions results in 4 LE usage with 5.6 ns delay
assign Y=A|A;
assign Y=A|A|A;
assign Y=A|A|A|A;
assign Y=A|A;
assign Y=A;
assign Y=A;
assign Y=A|A;
*/
endmodule

The resulting logic is 13 LE. If I minimize the functions by hand, a not difficult task, and describe the logic with boolean functions, I obtain the same circuit that only uses 4 LE and is also faster.

It looks like the "default" statement is not working properly. In fact the testbench that I use shows that in every not specified case the output is fixed to a single value (actually 7'b0010010).

This is very starnge. How is it possible that Quartus does not understand that y[2] is always equal to A[2]?

Thanks for your help.