Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Combinatorial minimization

Dear all, I tried a simple Verilog code for a combinatorial function with 6bit input and 7bit output. I describe the logic with a case statement. Since only six input cases are significant (...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The response of the SR has been:

"

Synthesizer wills use a series of common algorithm to optimize the design, sometimes synthesizer will not fully optimize the function to minimize logic. These behaviors are common for all of the synthesizer tools in the market.

Designer should write the RTL code in optimize method.

"

It seems that there's no intention to improve the synthesizer.