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What I want to say here is that the human style is far more important than coding style.
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I'll clearly agree. It's obvious, that you can easily waste hundreds and thousands LEs by an unreasonable design structure, so you must not necessarily care about 9 of them. On the other hand, the capability of the synthesis tool to reduce a behavioral description to the respective minimal logic equations, is an important feature that we should be able to trust in.
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In this particulkar example, it happens that the 'full case statement' is something that many HDL designers do not suggest to use. If Quartus requires this kind of coding, this is something that will bring me to use other synthesizers (and good coding styles) when I need to obtain high performance circuits.
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In fact, also IEEE 1364.1
ieee standard for verilog register transfer level synthesis suggests
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The use of the full_case and parallel_case attributes is generally not recommended.
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The reason for this suggestion is quite simple - avoiding simulation mismatch. For the time being, it can be handled by the alternative default statement, as in my example.
But I agree, that the behaviour of the Quartus synthesis tool in this point is unreasonable and should be fixed. I also don't exactly understand how it's brought up. I'm curious to hear the answer to your service request.
Honored Contributor
