Combinatorial minimization

Thanks to josyb for re-establishing my confidence in the Quartus synthesis tool.

Apparently, it's less smart in handling Verilog code. I'm not that familiar to Verilog, but it seems to me that the behaviour reported by nplttr is not required by the Verilog specification. You can however make Quartus minimize the construct by applying a full_case synthesis attribute and commenting the default statement. To avoid simulation mismatch, the default statement must be enabled for simulation only.

(* full_case *) 
case (A)
6'b000001 : Y <= 7'b1000000;
6'b000010 : Y <= 7'b1111001;
6'b000100 : Y <= 7'b0100100;
6'b001000 : Y <= 7'b0110000;
6'b010000 : Y <= 7'b0011001;
6'b100000 : Y <= 7'b0010010;
// synthesis translate_off
default   : Y <= 7'bxxxxxxx;
// synthesis translate_on
endcase
end