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Altera_Forum
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14 years ago

Combinatorial minimization

Dear all, I tried a simple Verilog code for a combinatorial function with 6bit input and 7bit output. I describe the logic with a case statement. Since only six input cases are significant (...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I think this has to do with the fact that all the default cases (i.e. everything that doesn't decode in the case statement) needs to be handled and the underlining technology are lookup tables. A is the input to the lookup table, Y is the output and the output cases are defined within the lookup table by the various outputs you coded. When you manually encoded the Y outputs you created functions that don't have default fall-throughs and as a result that didn't need to be encoded into the LUTs. I recommend reading the HDL synthesis guidelines in the Quartus II handbook, it probably does a better job explaining this that I just did.