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Yeah. I had also seen this kind of implementation but I didn't know there were a preference for this. Thanks anyway. I will test it.
As I mentioned in my former posts, I want to build a bidirectional interconnection network between some processors and some memories. This is just sample of my interconnection and I wanted to solve the combinational loop issue.
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Point taken. Buses between chips is one of the few cases where bidirectional lines may make sense since it saves board traces. Of course, you lose the possibility of sending and receiving at the same time and will have all sort of coordination issues unless you have one master.
I think the case statements (or if/else) actually make the code much more clear since it makes it obvious what the outputs are for a given set of inputs (SW and RW in your case).
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