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Altera_Forum's avatar
Altera_Forum
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8 years ago

Combinational Loop In VHDL synthesis

Dear all I've been working on a project in which I build an interconnection network with similar modules. Each module has 4 inout dataports. Also they have two control ports, one for R/W (Read or ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Yeah. I had also seen this kind of implementation but I didn't know there were a preference for this. Thanks anyway. I will test it.

As I mentioned in my former posts, I want to build a bidirectional interconnection network between some processors and some memories. This is just sample of my interconnection and I wanted to solve the combinational loop issue.