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Honored Contributor
Honored ContributorCombinational Loop In VHDL synthesis
Dear all I've been working on a project in which I build an interconnection network with similar modules. Each module has 4 inout dataports. Also they have two control ports, one for R/W (Read or ...
Altera_ForumHonored Contributor
Honored ContributorYes - best case is the design matches your RTL simulation results. Worst case it takes a long time to simulate and doesnt tell you alot.
Using the RTL only (using best practice) and good timing specs, I have never run a post synthesis simulation - as there has never been a need.
