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Honored Contributor
Honored ContributorCombinational Loop In VHDL synthesis
Dear all I've been working on a project in which I build an interconnection network with similar modules. Each module has 4 inout dataports. Also they have two control ports, one for R/W (Read or ...
Altera_ForumHonored Contributor
Honored ContributorIs there any reason you are running post synthesis netlist simulation? With a good synchronous design and good timing analysis netlist simulation should not be needed.
