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Altera_Forum
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8 years ago

Combinational Loop In VHDL synthesis

Dear all I've been working on a project in which I build an interconnection network with similar modules. Each module has 4 inout dataports. Also they have two control ports, one for R/W (Read or ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I did what you say and there is no combinational any more. But this time the top level inout ports have changed to buffers in the .vho netlist file.

For now the interconnect is internal to the FPGA. But later I might move everything to a board with separate memories.