Honored Contributor
Honored ContributorI think you are confusing several things here:
1. VHDL is just a high level language, and is designed as a modelling language. VHDL can be compiled by synthesis tools to logic if the VHDL describes a logic circuit. There are many VHDL constructs that will not map to real hardware, because VHDL is a modelling language so can also be written as non-synthesisable models. 2. Combinatorial is the same as asynchronous. Synchronous would mean a circuit with a clock. 3. Things cannot just be connected and everything be "fine". Did you think about what circuit you were trying to create? what is the purpose of the design? because VHDL is a modelling language you should first know what circuit you are rtying to create, and this is usually done before writing any code - on paper, or in a document or something. 4. VHO file is usually some form of compiled version of your code. You dont need it to simulate the design - the VHDL can be simulated directly. 5. Testbench ports can be any type you want. Types are just a VHDL construct to make the code easier to understand. At the end of the day, each bit will be it's own wire, so types have nothing to do with the final circuit. I cant really see what your code is supposed to do, other than connect different ports to each other. Its doesnt seem to serve much purpose. What is it supposed to do? Have you thought about making a synchronous design? FPGA fabric is really meant for synchronous circuits.
