Combinational Loop In VHDL synthesis

Thanks for the reply. Asynchronous? I'm intrigued. This is just a combinational circuit. How can it be asynchronous or synchronous at all? I used inout ports because I was assuming I would just connect them and everything would be fine. I missed the point that there is no bidirectional signal in VHDL and such thing would infer a lot of tri-state buffers.

Speaking of the vho file, I tested another module ( a simple cordic rotation) and the vho didn't change the signed ports to std_logic_vector(s). Actually, the conversion you mentioned was done inside the file (signed to std_logic_vector conversion). Now imagine I have a vho file with those std_logic_vector ports. But my testbench has signed ports and there would be a conflict. Should I change the testbench ports to std_logic_vector? Will the results be valid in that case?