Combinational Loop In VHDL synthesis

Why do you want inout ports? FPGA fabric cannot support inout, they will be synthesised as separate in and out ports with muxes. Only IO pins can be inout. You should really separated them in to separated in and out ports.

A combinatorial loop occurs when you have asynchronous logic that forms a loop. I cn only assume that this has happened somewhere with your circuit. This logic is unlikely to work and/or may become some kind of oscilator.

The std_logic_vectors appear because the signed data type is really only a VHDL abstract construct. In reality you will only get 1's and 0s, so the VHO only gives you std_logic_vectors. It is functionally identical to the signed type, except you'll need the type conversion in VHDL (which has no affect whatsoeveer on the logic implemented).

There must be some combination in your code that allows a logic loop. These are bad. I suggest a re-design is needed. Why have you got an asynchronous circuit? why isnt it synchronous?