Honored ContributorHi,
I need to add an external clock of 600MHz in SOPC Builder. But, the software allows until 500MHz. "Error: clk: clockFrequency (600000000) out of range (1,500000000)" So, I need to multiplicate the system clock (50MHz), but how to do this in SOPC ? Please, help me. :confused:
Honored ContributorWhat FPGA are you targetting? 600MHz seems a lot for an SOPC system. (or any FPGA design, in fact)
Honored ContributorThis is a Cyclone III (EP3C25F324).
Can't I do it ???Honored ContributorI want to add a external clock (LVDS data) , and his rate is 50 MSPS (12 bits = 600 MHz).
It's possible, a Texas Instruments kit reads this signal with a Xilinx.Honored ContributorIt's doable, but you won't be able to use a 600 MHz clock in a Cyclone III.
Instead, you'll need to use a 300 MHz clock and DDIO to get two bits per clock. http://www.altera.com/literature/ug/ug_altddio.pdfHonored ContributorAh, I totally forgot about the SOPC part.
You can't just feed the 600 Mbit/s signal comming from the FPGA into the SOPC. You need to write a component that receives and deserializes (and there's quite a bit to it) the 600 Mbit/s signal into 12 bit @ 50 MHz and then feed that into the SOPC.
