Clocking with Cyclone 10 Hard IP for PCIe, NIOS II processors, and mSGDMA.

I have a project with several IP blocks in platform designer: Cyclone 10 Hard IP for PCIe, NIOS II, mSGDMA, emif, onchip memory, IOPLL, and LVDS. In Intel's example design for Hard IP for PCIe expres...