Forum Discussion
KRoma6
New Contributor
New ContributorClocking with Cyclone 10 Hard IP for PCIe, NIOS II processors, and mSGDMA.
I have a project with several IP blocks in platform designer: Cyclone 10 Hard IP for PCIe, NIOS II, mSGDMA, emif, onchip memory, IOPLL, and LVDS. In Intel's example design for Hard IP for PCIe expres...
EBERLAZARE_I_Intel
Regular Contributor
Regular ContributorHi,
You could try below design example:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-a10-pcie-avst.pdf
Also, more reference on the clocking information:
