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Honored Contributor
Honored ContributorClocking question: modelsim
Hello, I came across a matter which I do not understand: always@(posedge clk or negedge reset) begin
if(!reset) ....
When clk does not clock I change reset from high to low and .....
Altera_ForumHonored Contributor
Honored ContributorThank you so much! Very informative and thorough answer. I use Cyclone-3, and use the "right" code. Tried moidelsim several times and it seems it was an intermittent problem of modelsim, or I did something wrong during simulation.
You raised one thing which was bothering me some time ago with your second, "wrong" example. When posedge of clk happens, what will happen if this "if (clk)" is used in the body of always? I thought to use it before, but decided that it may cause metastability of the circuit. Please advise.
