Clock skew from using global and local routing

The fitter should not be doing that. I would try to identify what is being put onto the global and what is not, and see if something jumps out, such as "All the registers in block A are put onto local while everything else is global". It shouldn't be random. The only things I can think of are:

- Partitions might cause this, if some are post-fit. Maybe when they were compiled, the fanouts for the partition were put on local/global while the later compiles the other one was chosen. I've never seen that happen, but just a thought that's easy to determine(you would have had to manually create partitions)

- Global buffers in the design. Doubtful, but maybe they exist, which can cause behavior if they don't cover all the fanouts. Also look for "Global" assignments in the Assignment Editor.

- There is a case where it will demote a signal from a global, but that is when it is used as a clock elsewhere. For example, let's say you have a register clocked by the global clock, but that register feeds the clock port of other registers. This causes huge clock skew and all sorts of timing problems. I've seen Quartus demote the clock route to that first register to reduce the skew, but does add some issues for transfers to/from that register. That being said, it would only be a register or two.

One thing to try is assign Global = On for the source. For whatever reason it's occuring, that may clean it up.