Forum Discussion
SKinz
New Contributor
New ContributorClock, PLL, driver placement
I have a design that places plls and clock drivers with a little bit interface planning in Quartus 18.0.1. But, Quartus 18.1 fails to find a placement solution on the same design. Using the interface...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorMay I know the below.
From the above you mean to say the design pass on Quartus 18.0.1 and fails on Quartus 18.1 .
If the above statement is correct may I get the below details
Which Quartus verion ( Pro or std)
Error Message
Device,
If possible sample design
