Forum Discussion
ChristophD
New Contributor
New ContributorClock pessimism removal
I need to time constrain a source-synchronous interface between a Cyclone10GX and a LVDS camera interface running at ~596MBPS. (I'm using Quartus prime pro 19.3)
The FPGA drives out a 124MHz clk ...
SyafieqS
Super Contributor
Super ContributorHi Dietz,
You may refer to link below related to Design Guidelines for Implementing LVDS Interfaces in Cyclone Series Devices and Timing Pessimism
1. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an479.pdf
ChristophDHi SyafieqS_Intel,
I know these documents and the second describes what the timing pessimism (common clock path pessimism) is and that it is removed during timing analysis. Usually there is a line in the timing analyzer report (and in the Timing analyzer GUI) that shows the removed timing pessimism. But not in this case, though both signals share most of the clock path (cf. attached file "NoPessimismRemoval.txt") . What's wrong?
Best regards
Christoph Dietz
