New Contributor
Super ContributorHi Dietz,
You may refer to link below related to Design Guidelines for Implementing LVDS Interfaces in Cyclone Series Devices and Timing Pessimism
1. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an479.pdf
New ContributorHi SyafieqS_Intel,
I know these documents and the second describes what the timing pessimism (common clock path pessimism) is and that it is removed during timing analysis. Usually there is a line in the timing analyzer report (and in the Timing analyzer GUI) that shows the removed timing pessimism. But not in this case, though both signals share most of the clock path (cf. attached file "NoPessimismRemoval.txt") . What's wrong?
Best regards
Christoph Dietz
