Honored Contributor
Honored Contributor150MHz might be pretty high. The interface can tolerate +/- 3.333ns of clock/data skew.
Anyway: create_clock -period 40.0 [get_ports in0_clk] inclk_25mhz ... create_clock -period 6.666 [get_ports in7_clk] inclk_150mhz create_generated_clock -name outclk_25mhz -source [get_ports in0_clk] out_clk ... create_generated_clock -name outclk_25mhz -source [get_ports in7_clk] out_clk set_output_delay -max -clock outclk_25mhz# .### out_d set_output_delay -min -clock outclk_25mhz# .### out_d ... set_output_delay -max -clock outclk_150mhz# .### out_d set_output_delay -min -clock outclk_150mhz# .### out_d set_clock_groups -exclusive -group {inclk_25mhz outclk_25mhz} ... -group {inclk_150mhz outclk 150mhz} The# .### are the values you need to enter. Also note that there is no clock inversion in these constraints, which is incorrect. We're basically saying that the same clock that launches the data latches it and they are aligned. If the launch and latch clocks are aligned, then the data delay will need to be a half period longer to balance your setup and hold requirements. (This falls into my earlier question of making sure you can do a single source synchronous interface without the clock muxes. That's the difficult part. There is an app note on the website that covers this...)
