Clock multiplexing and SDC

>Just for clarification, you have 8 clocks coming in on 8 different pins?

>Do they go through PLLs, or are they muxed together?

The 8 clocks come in on 8 different pins and do not go through a PLL. The input clocks vary from 25MHz to 150MHz and have a 50/50 duty cycle. The data changes on the falling edge. The PCB traces have been equalized so that the skew between the incoming data and clock should be minimal.

The input data is first lateched and then multiplexed to an output port together with the incoming clock. Something like this:

// input register

reg[7:0] in_r[0:7];

always @(posedge in0_clk)

in_r[0] <= in_d;

// selection

case (sel)

3'b000 : {out_d, out_clk} <= {in_r[0] in0_clk};

3'b001 : {out_d, out_clk} <= {in_r[1], in1_clk};

.

.

3'bxxx : {out_d, out_clk} <= {in_r[x], inx_clk};

endcase

The out_d and out_clk are then passed through DDIO registers to invert the clock and to edge allign the data to the clock close as possible.

This seems to run fine, but I do not understand how to set-up the constaints in the SDC file.

Thanks for the help

Richard