Clock multiplexing and SDC

Make sure you understand source synchronous assignments on a single data stream(i.e. take 5 minutes to do a simple test case with a clock and data going off chip, and constrain it and understand how it's being analyzed, unless you've already done this or feel comfortable with it already.) Then move onto the clock muxing.

Just for clarification, you have 8 clocks coming in on 8 different pins? Do they go through PLLs, or are they muxed together? The 8 create_generated_clock assignments on the output port show that 8 different clocks go out this port, and what they are related to. (If the 8 clocks go through a PLL or register, then you will have a generated clock there, and the clock out create_generated_clock assignments will be generated from those generated clocks, not the input pins.) Show the constraints you have and the problem you're encountering, which might be useful.