Honored Contributor
Honored Contributor>1) I hope you're not expecting clean behavior when switching between >clocks(glitch free), or at least have put a lot of analysis to these cases.
Glitches are not a problem in this design. >3) Do you invert/phase shift the clock 180 going off chip, or are you sending >the clock and data edge aligned? The output clock is inverted using a DDR register and inverted clock + data are alligned using DDR registers. Perhaps I was not clear enough in my previous posting. The data and clock should be synchronous (edge aligned) as seen from the output port of the FPGA and not as seen from the different input ports. It also does not matter if there is a delay inside the FPGA, as long as the output data and clock are alligned. For the generated clocks do I need to specify the output of the clock multiplexer as the source, or do I need to specify the input clock port as the source? Thanks, Richard.
