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Altera_Forum
Honored Contributor
Honored ContributorClock gating with enable or not
Here is a n00b question from one which is rusty in VHDL: The statement is not to gate the clock, but is the following considered clock gating? ena is a synchronous enable signal.
proces...
Altera_ForumHonored Contributor
Honored ContributorAll signals inside branch for clock transition are synchronus.
even if it enable clock signal per LAB. (okay this signal could come along with active clock-edge?) I think about synchronus and synchronus, and clock-gating at source or enable clock per flip-flop. does documentation juggle the termins so free? Hope no, cause for each case we have a nice figures for clarification. but it is terrible. It is due to optimization technique.
