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Altera_Forum's avatar
Altera_Forum
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10 years ago

Clock gating with enable or not

Here is a n00b question from one which is rusty in VHDL: The statement is not to gate the clock, but is the following considered clock gating? ena is a synchronous enable signal. proces...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

All signals inside branch for clock transition are synchronus.

even if it enable clock signal per LAB. (okay this signal could come along with active clock-edge?)

I think about synchronus and synchronus, and clock-gating at source or enable clock per flip-flop.

does documentation juggle the termins so free? Hope no, cause for each case we have a nice figures for clarification. but it is terrible.

It is due to optimization technique.