Clock gating with enable or not

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Here is a n00b question from one which is rusty in VHDL:

The statement is not to gate the clock, but is the following considered clock gating? ena is a synchronous enable signal.

Is this above functionally the same as the line below? Syntax-wise it seems so, but it starts to feel awfully like gating.
if clk'event and clk='1' and ena='1' then

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Compilers are good here and I assume they will not gate clock. But why divert away from simple template of first code to mislead the compilers?