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Altera_Forum's avatar
Altera_Forum
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10 years ago

Clock gating with enable or not

Here is a n00b question from one which is rusty in VHDL: The statement is not to gate the clock, but is the following considered clock gating? ena is a synchronous enable signal. proces...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

You can use synthesis attribute direct_enable set to false but you can get lut instead of sload signal for LE

And replace checking for clock edge with rising_edge cause later provide real 0 to 1 compare it with X to 1 in your code

Then using synchronous signal- you should allow it in synthesis.

You can try utilize both sclear and sload so tool understand synchronous