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Once you constrain the clock signals (create_clock or create_generated_clock), TimeQuest will automatically analyze any paths between registers, including the clock enables. No point in adding set_max_delay constraints.Sometimes, you can/need to add multi-cycle constrains to _relax_ the analysis.
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Indeed the tool should check all paths between registers.
clock enable path will all be checked provided either it is generated internally on the clock or if it input pin then you must use set_input_delay correctly. If it is asynchronous then you are in trouble and will need to synchronise it and manage the resulting latency.
We should first give the tool a go and if it fails to meet timing then we got so many options to interfere but this is a job not for beginners really because in their case it is more likely that their design is the cause of trouble and it will be better to identify the issues than to beat the tool's head.
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