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Altera_Forum's avatar
Altera_Forum
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13 years ago

Clock Enable to Clock Constraint

I have a design with clock enables going to almost all the flops in the design. I am worried that the clock enable may arrive late causing timing issues. How do I constrain the clock enable to d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Once you constrain the clock signals (create_clock or create_generated_clock), TimeQuest will automatically analyze any paths between registers, including the clock enables. No point in adding set_max_delay constraints.Sometimes, you can/need to add multi-cycle constrains to _relax_ the analysis.