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I have a design with clock enables going to almost all the flops in the design.
I am worried that the clock enable may arrive late causing timing issues.
How do I constrain the clock enable to detect this violation in quartus?
I can't come up with the sdc syntax.
On a related note, should i also set max fanout constraint to prevent this so that the source
gets duplicated.
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Either you or the tool can do replication. You can also set your max fanout to update default value. But I will worry about all these things when the tool fails to meet timing or the design does not work. We depend on these tools and make our living on them and the guys behind them have pre - done much of the work for us to be automated.
If however you do run into fanout trouble then your thinking is right. This is more likely with reset signal than with clock enable.
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