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MicroDick's avatar
MicroDick
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2 years ago

clock control intel FPGA IP is not correct in quartus prime pro 23.4

I have created a project in quartus prime pro 23.4 ant I have used clock control intel FPGA IP as a MUX for clock.And When I run synthesis error encouted. Error(13224): Verilog HDL or VHDL error at ...
EthanLi's avatar
EthanLi
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

As mentioned above, the input clkselect should be 1bit while you defined it as 2 bit.

Thanks,

Ethan

MicroDick's avatar
MicroDick
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2 years ago

Thanks, I know what this message means , but this Verilog file is automatically created by Quartus prime ,which is why i am confused