Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Clock Constraints for a Clock signal created with a Nios software-driven Output Port

I have a test bed for my DSP logic design in a Cyclone III, and in this I use the Nios2 processor to control the test process (it is easier for me to test it using the NIOS2 debugger) The DSP ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I think you can make the DSP block as a Custom component which acts as an avalon slave to Nios II processor rather than driving a clock from Nios II to DSP Module

Regards

M Kalyansrinivas