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Altera_Forum
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14 years ago

Clock Constraints for a Clock signal created with a Nios software-driven Output Port

I have a test bed for my DSP logic design in a Cyclone III, and in this I use the Nios2 processor to control the test process (it is easier for me to test it using the NIOS2 debugger) The DSP ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Generating a clock from FPGA logic is a bad idea, because the glitches caused by the LUT can be seen as extra clock edges by some cells and would make your logic crash or behave strangely. If possible, it is far better to use the main clock and only control a clock enable signal from the CPU.