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DNguy4's avatar
DNguy4
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

clock buffer

Hi, I implement a one to two clock buffer in my design and feed to two different pins of a module. I need to have two distinct clock names so that we can control max/min delay between them in my ti...
a_x_h_75's avatar
a_x_h_75
Icon for Contributor rankContributor
7 years ago

So the rising/falling edge of out2 must be within 5ns of out1? Or are you trying to design something where the edges are locked 5ns apart?

If it's the latter then you need a PLL with multiple output clocks. As I mentioned before, you need to ensure this by design. Timing constraints will only tell you whether your design meets timing.

Cheers,

Alex