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DNguy4
Occasional Contributor
Occasional Contributorclock buffer
Hi, I implement a one to two clock buffer in my design and feed to two different pins of a module. I need to have two distinct clock names so that we can control max/min delay between them in my ti...
a_x_h_75
Contributor
ContributorTime Quest will not recognise out1 or out2 as clocks unless they feed a design element that is clocked - such as a flip-flop or PLL.
If you need to analyse the delay out then you'll need a set_output_delay command. However, I get the impression you're trying to control the delay out using timing constraints. Is that right? You need to do this by design, not through the use of timing constraints.
Cheers,
Alex
