Forum Discussion
Altera_Forum
Honored Contributor
17 years agoTo be sure you've constrained everything, run "Processing --> Start --> Start Classic Timing Analyzer Constraint Check". TimeQuest users should run Check Timing and Report Unconstrained Paths.
I recommend that you not use any of the project-wide timing constraints for fmax or I/O. Constrain each non-PLL clock individually. Constrain each pin individually. Anything you miss will then be caught by the timing constraint check. Someone maintaining your design later (even if it is you) will have more confidence that you really intended the constraints you used and didn't overlook something like a particular input pin needing a tsu different from the project-wide setting.