Classic Timing Analyzer: tsu calculation backwards?

Thanks Rysc/Brad. I'm always amazed by your expertise. I'm also amazed how you can spend so much time in these forums. Are you exployed by Altera by any chance?

I will study your responses in more detail tonight. For now, based on your explanations, it seems only external timings need to be constrained (input pin to input registers and output registers to output pin - adjusted for the requirements of the external devices), not timings between internal modules? I have a large number of internal modules in the form of Verilog, LPMs etc and i have no idea what kind of timings these modules need. This is why i just punched in 0.5 ns for tsu and th in the GUI - clearly i don't know what i'm doing but i'll figure it out soon, i'm sure...