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Hello all,
I have some verilog code that has many basic arithmatic symbols in it (+,-,*,/). Obviously the simple and perhaps also wise thing to do is to replace such operators with Mega-Wizard modules but I have many of them and not allways in the same bit size. my problem is this: most of the calculations are with signed (2's complement) numbers and I want to set the default synthesis of operators as signed operations. this way I would know for sure - no matter what board I'm using that when I write a+b it's synthesized as signed adder.
PS the same goes also to simulations in Modelsim if anyone knows.
Thanks,
Ayal
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Hi,
have a look to the improvements coming with Verilog 2001. As far as I know signed and unsigned is directly supported. Have a look to :
http://www.asic-world.com/verilog/verilog2k1.html Kind regards
GPK
Honored Contributor
