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Altera_Forum's avatar
Altera_Forum
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16 years ago

choosing default synthesis for arithmatic operators

Hello all, I have some verilog code that has many basic arithmatic symbols in it (+,-,*,/). Obviously the simple and perhaps also wise thing to do is to replace such operators with Mega-Wizard ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Have you taken a look at the templates menu in Quartus II? It has a bunch of arithmetic templates for Verilog and VHDL that might show you how to code those operators to ensure you get what you want.

Have a source file open and then go to "Edit" --> "Insert Template" --> then navigate to the language and logic type you want.