Chip-planner block names inside the PLL

What do these two blocks indicate in the chip-planner?

PLL DPA Output and PLL LVDS Output

Anybody know of a link to Altera's documentation on this kind of information related to the chip-planner? E.g. Arria V handbook says PLLs have 18 counters. How do I know which counter is 18th and which one is the first in the chip-planner? I am trying to add a location constraint to the counters for ALTLVDS instances in my design to work around an errata in the devices.