Altera_Forum
Honored Contributor
8 years agocheck_timing command (registers with no clock defined)
Hi guys
In quartus sdc "check_timing" documentation it says: "The no_clock check reports whether registers have at least one clock at their clock pin, and that ports determined to be clocks have a clock assigned to them, and also checks that PLLs have a clock assignment." This is really confuses me. First of all, if registers don't have a clock, they will be automatically removed in synthesis phase. consider this case: module regs_noclock ( input clk, input data_in, output data_out ); reg q0,q1; wire genclk assign genclk = q0; assign data_out = q1; always @(posedge clk) q0 =~q0; always @(posedge genclk) q1 = data_in; endmodule I didn't generate any sdc for this example. the genclk is undefined( or that's what i understood) still when I run the command "check_timing -include {no_clock}" it return 0. so the genclk is know for the tool as a clock. the question is : in which case timequest reports registers with no clock defined?
Maybe this will give a clear idea: in xilinx, they have the following message: "there are 42 reg/latch with no clock driven by root clock pin" thanks