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Altera_Forum
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10 years ago

Channel Deadlock Debugging

I've developed a design in which there are 4 NDRange kernels all running concurrently on the FPGA and communicating with each other via the Altera OpencL Channels extension. There are many channels i...
Altera_Forum's avatar
Altera_Forum
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9 years ago

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Hello, now I met the same problem with you! Have you solved your problem?How?Thanks!!

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If you see my previous post, I could solve the issue by re-ordering how the data is taken out of the pipes/channels. Unfortunately due to how my kernels were required to execute I abandoned this design and moved towards one that used local memory to transfer data.