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Altera_Forum's avatar
Altera_Forum
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16 years ago

Changing SOPC File Location

Hi,

I'm working on a project involving multiple Quartus projects that share common components. All of the common verilog components are shared in an external folder, but I can't find any way to share SOPC Builder files. I would like to move the .sopc file and the Nios IDE projects to a common directory, then simply include them in any Quartus projects that need them.

I tried moving the .sopc file, opening it in SOPC Builder, and generating the system but I ran into errors saying the *_setup_quartus.tcl script couldn't find my project. I can't quite see what SOPC Builder needs from my project since the system doesn't have any knowledge of my other hardware until I connect it at the top level.

Has anyone had any success doing this before? I could copy the files into each of the Quartus projects' folders, but I would like to maintain a common base of changes across all of them - everything is checked into SVN and I'd like to be able to maintain consistency across the projects by updating to a new revision. Thanks.

16 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    It looks ok I think. I just deleted and recompiled the .hex file and it still doesn't program. I'm going to try recompiling the project now with the .hex file already built to see if that helps.

  • Altera_Forum's avatar
    Altera_Forum
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    Oh I should mention one other thing.

    Are you aware that if you make a change to the HEX file after compiling the Quartus Project, it's necessary to run the "Update Memory Initialization File" routine and the assembler to create a new FPGA programming file?

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    Bingo. Thanks for all of your help! This is going to make things so much easier.

  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Oh I should mention one other thing.

    Are you aware that if you make a change to the HEX file after compiling the Quartus Project, it's necessary to run the "Update Memory Initialization File" routine and the assembler to create a new FPGA programming file?

    Jake

    --- Quote End ---

    Ahhh, that could do it. Thanks!
  • Altera_Forum's avatar
    Altera_Forum
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    If you've got the project set for "Smart Compilation", it should automatically figure out that these are the only steps that need to be done. Then you just click the compile button and it should just run those two steps.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    I had turned that off a while ago. If I remember correctly I couldn't use SignalTap with it on (I'm using the web edition of Quartus). That should definitely save a ton of time though, since I'm not using SignalTap now anyway. I can just turn it back off if I need to use it. Thanks.