Cascading PLLs in Stratix-III

Well I just did a little test compile with cascaded PLLs and it worked fine. I suspect your problem is this (from page 6-28 of the Stratix III device handbook):

--- Quote Start ---

The input and output delays are fully compensated by a PLL only when they are

using the dedicated clock input pins associated with a given PLL as the clock source.

Input and output delays are not compensated when cascading two adjacent top or

bottom PLLs even if they are using dedicated routing for cascading. For example,

when using PLL_T1 in normal mode, the clock delays from the input pin to the PLL

clock output-to-destination register are fully compensated provided the clock input

pin is one of the following four pins: CLK12, CLK13, CLK14, or CLK15. When an

RCLK or GCLK network drives the PLL, the input and output delays may not be fully

compensated in the Quartus II software.

--- Quote End ---

If you are trying to force the second PLL to do feedback compensation, it is wanting the clock input to be on an input pin.

Jake