Forum Discussion
Altera_Forum
Honored Contributor
11 years agoCarry in on a 4 bit adder
Hi I have a add in verilog to add 2 times 4 bit A+B and a carry to get a result of 4 bit + 1 carry out I do use Quartus 14.0 and a MAX10 I do have this verilog code: module add_4bit...
Altera_Forum
Honored Contributor
11 years agoYes same result in the Technology Map... I have tried different way to force it but no luck
I also found a this info at "https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_low_level.pdf" "The cin port of the CARRY_SUM primitive cannot be fed by an input pin." Guess it's not possible to route the cin / cout in the normal routing