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Altera_Forum
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10 years ago

Carry Chain used as delay line - Problems with supllying LUT-s with ones and zeros

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I have used original TDC (adder based) and everything is done as I have explained in earlier posts. Yeah measurement results are looking very good. Delay line was 128 cells long. I was adding 96 ps of shift in every step. Now my main problem is how to make tests with better resolution; my Cyclone IV is only resource for that so I need to see if I can do some better measurements.