Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Carry Chain used as delay line - Problems with supllying LUT-s with ones and zeros

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Pretty impressive and I would say linearity is good enough... According to most of the papers I have read testing is done by means of density test for a given time delay. I think sort of pulse train with random noise modulation (inducing jitter) would be good enough.... I hope my description is clear enough...

Let me know if you still use your original TDC (adder based) with the register in the front? Did you try to adapt and test the code I have posted? Let me know if you need wysiwyg doc for your cyclone series...

According to the chart it looks like the delay line is about 80 cells?