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Altera_Forum
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10 years ago

Carry Chain used as delay line - Problems with supllying LUT-s with ones and zeros

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Thanks for this interesting papers! I am currently testing my TDC and here is my transfer function:

http://www.alteraforum.com/forum/attachment.php?attachmentid=12292&stc=1

One thing bothers me; I was testing TDC as I have explained earlier with dynamic phase shift from PLL. I am shifting with external push button, one push means one shift but I am not quite sure that dynamic shift is done every time so I am looking to find a way to be sure about that. This TDC transfer characteristics was done in hope that every time when I pushed the button, signal has been shifted for another 96 ps.