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Altera_Forum
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10 years ago

Carry Chain used as delay line - Problems with supllying LUT-s with ones and zeros

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_Forum's avatar
Altera_Forum
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9 years ago

For you using FFs latch delay-line's result, i think you can use SignalTap II to test your TDC. It's better than you current way.