Can't use testbench in Modelsim - error loading design

Tricky, thank you. You're right, it's best to open these files in Modelsim itself and not through Quartus.

I have actually found a solution to this, I'll post it here in case others run into the same problems: (assuming vhdl and not verilog)

1. If you have a BDF file like me, use Quartus to create an HDL file from it (file -> create/update -> create HDL file...)

2. Open a project in modelsim

3. Add all the vhd files in your design, include of course the main HDL file

4. Open the main HDL file so that the code appears (you can edit it, etc.)

5. In the menu, click on source -> show language templates

6. In the new window that just opened, double click create testbench

7. Write your testbench code

8. Compile the files, click simulate, and choose to simulate the testbench file in your work library